1. Field of the Invention
The present invention relates to a pattern generator for use in a semiconductor test device for generating random pattern data to supply to a semiconductor device to be tested.
2. Prior Art
The construction of a conventional pattern generator for use in a semiconductor test device will be described with reference to FIG. 4.
The pattern generator for use in a semiconductor test device comprises an address generator 10, a sequential pattern memory 11, a random pattern memory 12 and a selector 13. The address generator 10 generates address data 10a sequentially or at random in accordance with a previously written program, and supplies them to an input terminal of the sequential pattern memory 11 or an input terminal of the random pattern memory 12.
The address generator 10 is programmed to output a selection signal 10b in the manner of allowing the selector 13 to select data 11a outputted from the sequential pattern memory 11 when it generates the address data 10a sequentially or allowing the selector 13 to select data 12a outputted from the random pattern memory 12 when it generates the address data 10a at random.
Respective random pattern data are stored in respective addresses of the sequential pattern memory 11. The sequential pattern memory 11 is a memory (for example, magnetic tape device, etc.) for executing read and write of data by accessing values of consecutive address data (sequential access) such that values of the address data 10a are incremented one by one such as . . . .fwdarw.4096.fwdarw.4097.fwdarw.4098.fwdarw.4099 . . . or same values of the select data 11a are repeated such as . . . 4101.fwdarw.4101 .fwdarw.. . .
In cases where the address data 10a generated by the address generator 10 are consecutively outputted, the random pattern data 11a stored in the sequential pattern memory 11 are outputted from the sequential pattern memory 11 in accordance with input address values and inputted a first input terminal of the selector 13.
The random pattern memory 12 is a memory (random access memory such as a dynamic RAM, a static RAM) which can arbitrarily access respective addresses, and random pattern data are previously stored in respective addresses like the sequential pattern memory 11. The random pattern memory 12 outputs the random pattern data 12a which are stored therein in accordance with values of address data 10a outputted from the address generator 10 and inputs to a second input terminal of the selector 13. The selector 13 selects either the input data 11a or input data 12a in response to the selection signal 10b and outputs the selected data as random pattern data.
The pattern generator for use in a semiconductor test device writes a program on the address generator 10 appropriately in accordance with the content of test or a semiconductor device to be tested and tests on the semiconductor device to be tested using the random pattern data stored in the sequential pattern memory 11 or the random pattern memory 12.
However, the sequential pattern memory 11 has generally large capacity but it is late in time for outputting data stored in addresses after the addresses are specified, namely, it is a so-called slow speed memory. On the other hand, the random pattern memory 12 is a high speed memory but it has small capacity compared with the sequential pattern memory 11. Accordingly, the conventional pattern generator for use in a semiconductor test device requires an expensive memory which runs at high speed and has large capacity for generating random pattern data of high speed with large capacity, and hence it has been difficult to allow the pattern generator to run at high speed, to be small sized and to manufacture at low cost.